Block Turbo Code decoder (BTC)

Performs TPC decoding as defined in the IEEE 802.16 and 802.16a standards.
Block sizes from 64 bits to 4 Kbits, 64 possible product codes.
Support of external early termination + optional internal early termination at even/odd half iterations for higher    throughputs.
The following rates had achieved for FPGAs:
Single-SISO option achieves a data rate of 9 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 28 Mbps.
Four-SISO option achieves a data rate of 36 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 112 Mbps.
Eight-SISO option achieves a data rate of 72 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 225 Mbps.
Sixteen-SISO option achieves a data rate of 144 Mbps with five iterations using (64,57)^2 code, average rate can achieve a 450 Mbps.
Single-SISO option requires 721 FFs, 74,668 RAM bits (single port).
Fully synchronous design using a single clock.
Simple and efficient interface to control the decoder operation.
Available for ASIC/FPGA designs as verilog source code or as netlist.

Applications
The TPC Encoder core is designed to operate in local multi-point distribution service (LMDS) and multi-channel
multi-point distribution service (MMDS) communication systems.
The core is especially useful for those communication links that require high data rates, low latency, high code rates,
high spectral efficiency, and a high degree of forward error correction capability.
Turbo Product Codes offer a higher performance alternative to Reed-Solomon or Reed-Solomon concatenated with Viterbi
error correction methods.

Functional description
This core performs two-dimensional product code decoding with constituent codes that are either extended Hamming codes or simple parity codes. The decoder double buffer at its input to support continuous decoding, the decoder is working on one buffer while the host writes the second buffer. The decoder supports early termination to save decoding time. The decoder shifts the recovered data out every half iteration, the decoder also generates an output address for each output bit to support the odd half iterations.

The core supports both extended Hamming and parity only constituent codes as listed in the table below:

The TPC decoder core supports 8 possible code types for each of the constituent codes for a total of 64 possible product codes.

Controlling the core
The core enable continuous packets decoding. A double buffer at the input enable decoding operation while the host writes the second buffer. The switching between the buffers is done automatically by the decoder. Internal buffers are 16 bits wide, each row holds 4 input symbols, from left to right (bits 15:12 are the first symbol and bits 3:0 are the 4'th symbol). The host should assert the tpc_start_decoding after it had finished to write a data buffer and the tpc_decoder_active signal is low. High tpc_data_out_valid signal indicates that the decoder is writing out the decoded data (information + parity) while high tpc_valid_data_out_valid signal indicates a valid information bits.

Code shortening
Code shortening provides a way to achieve exact packet sizes to match specific system level constraints. When shortened TPC codes are used, the actual data packet size is reduced by inserting zeroes into the encoded and decoded block. The zeroes are not transmitted over the communications link but are reinserted into the block prior to decoding. Both the effective block size and effective code rate are reduced by code shortening.

Ordering information
BTC decoder available as verilog source code or as EDIF netlist for Xilinx/Altera FPGAs families.
Delivery includes:

Verilog source code or verilog EDIF netlist.
Simulation environment.
Documentation.

For more information please contact us

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