 Performs
TPC encoding as defined in the IEEE 802.16 and 802.16a standards.
Block sizes from
64 bits to 4 Kbits, 64 possible product codes.
Fully synchronous
design using a single clock.
Low latency (4 clocks)
independent of code type.
Encoding algorithm
of 1 clock per 1 encoded bit.
Up to 8 Kbits of
internal buffering allows continuous encoding of packets.
Simple and efficient
interface to control the encoder operation.
Available as verilog
source code or as netlist.
Applications
The TPC Encoder core is designed to operate in local multi-point
distribution service (LMDS) and multi-channel
multi-point distribution service (MMDS) communication systems.
The core is especially useful for those communication links that
require high data rates, low latency, high code rates,
high spectral efficiency, and a high degree of forward error correction
capability.
Turbo Product Codes offer a higher performance alternative to
Reed-Solomon or Reed-Solomon concatenated with Viterbi
error correction methods.
Pin out
Core signal pinout
|
Pin name
|
Direction
|
Description
|
| clk |
input |
Clock that triggers all sequential
elements on its rising edge |
| reset_n |
input |
Active low synchronous reset |
| x_code[2:0] |
input |
Specifies 1 of 8 possible product
codes at x dimension |
| y_code[2:0] |
input |
Specifies 1 of 8 possible product
codes at y dimension |
| encode_en |
input |
Active high enables encoding
operation |
| data_in_en |
input |
Active high enable for input
data |
| data_in |
input |
Input data to be encoded |
| block_out_start |
output |
High during the first bit of
each output code block |
| block_out_end |
output |
High during the last bit of
each output code block |
| data_out_valid |
output |
High when output data is valid |
| data_out |
output |
Encoded output data |
| input_fifo_almost_full |
output |
High when input fifo is almost
full |
| input_fifo_empty |
output |
High when input fifo is empty |
Functional description
This core performs two-dimensional product code encoding with
constituent codes that are either extended Hamming codes or simple
parity codes. A product code works on an array of information
bits by encoding all of the rows followed by encoding all of the
columns. The column encoding is performed on both the original
information bits as well as the parity bits generated from the
row encoding. The following illustration shows the (8,4)x(8,4)
product code. Dij represent input data, the Hij represent parity
bits from the Hamming code and the Pij represent the overall parity
bits.
|
D11
|
D21
|
D31
|
D41
|
H51
|
H61
|
H71
|
P81
|
|
D12
|
D22
|
D32
|
D42
|
H52
|
H62
|
H72
|
P82
|
|
D13
|
D23
|
D33
|
D43
|
H53
|
H63
|
H73
|
P83
|
|
D14
|
D24
|
D34
|
D44
|
H54
|
H64
|
H74
|
P84
|
|
H15
|
H25
|
H35
|
H45
|
H55
|
H65
|
H75
|
H85
|
|
H16
|
H26
|
H36
|
H46
|
H56
|
H66
|
H76
|
H86
|
|
H17
|
H27
|
H37
|
H47
|
H57
|
H67
|
H77
|
H87
|
|
P18
|
P28
|
P38
|
P48
|
P58
|
P68
|
P78
|
P88
|
The input data array is filled
row-by-row from left to right. The encoded data is written out
row-by-row from left to right.
The core does not support the optional block interleaving listed
in the IEEE 802.16 standard.
The latency of the core from encode_en to data_out_valid is 4
clocks.
The Hamming code generator polynomials
for each block size are listed below:
|
n
|
k
|
Generator polynomial
|
|
7
|
4
|
X^3 + X + 1
|
|
15
|
11
|
X^4 + X + 1
|
|
31
|
26
|
X^5 + X^2 + 1
|
|
63
|
57
|
|
The core supports both extended
Hamming and parity only constituent codes as listed in the table
below:
|
x_code[2:0]/y_code[2:0]
|
x/y code
|
Code type
|
|
000
|
(8,4)
|
Extended Hamming
|
|
001
|
(16,11)
|
Extended Hamming
|
|
010
|
(32,26)
|
Extended Hamming
|
|
011
|
(64,57)
|
Extended Hamming
|
|
100
|
(8,7)
|
Parity only
|
|
101
|
(16,15)
|
Parity only
|
|
110
|
(32,31)
|
Parity only
|
|
111
|
(64,63)
|
Parity only
|
The TPC encoder core supports 8
possible code types for each of the constituent codes for a total
of 64 possible product codes.
Controlling the core
The core enable continuous packets encoding. An input fifo controls
the input rate into the encoder, the user should take care of
the input data timing using the input_fifo_almost_full, block_out_start,
block_out_end and input_fifo_empty. The latter signal indicates
that the amount of written data had an exact packet size.
A fundamental limitation of the core is that there is no way to
reset the contents of the RAM used in the y encoder.
If input_fifo_error occurred, the encoder must be flushed for
one data block before correct encoding can resume.
FPGA fitting results
| FPGA Usage/FPGA device |
Slices/LE |
Memory |
Frequency |
| Altera Stratix |
178 LEs |
8,640 memory bits |
135 MHz |
| Altera Cyclone |
178 LEs |
8,640 memory bits |
126.5 MHz |
| Xilinx Virtex2 |
93 slices |
2 block RAMs |
>150 MHz |
| Xilinx VirtexE |
95 slices |
3 block RAMs |
85.3 MHz |
| Xilinx Spartan2 |
95 slices |
3 block RAMs |
73.2 MHz |
Ordering information
BTC encoder available as verilog source code or as EDIF netlist
for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Verification
environment .
Documentation.
For more information please
contact
us
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