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 Compliant
with CMMB specifications, block size of 9216 bits, code rates
1/2 and 3/4.
Frame by frame programmability
of code rate and number of iterations.
Syndrome based LDPC
iteration stopping and indication.
ASIC and FPGA proven.
Throughput of 50Mbps
on FPGA platform.
Low power design.
Ordering information
CMMB LDPC decoder available as verilog source code or as EDIF
netlist.
Delivery includes:
Verilog
source code (optional VHDL) or verilog EDIF netlist.
Extensive
test bench environment.
C/Matalb
bit accurate model.
Detailed
ocumentation.
For more information please contact
us
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