 K=4
(8 states).
Rate 1/3, other
rates can be achieved with external puncturing.
Up to 6.7 Mbit/s
at full 8 iterations with Altera Stratix/Cyclone or Xilinx Virtex2.
Sophisticated early
termination mechanism to support power saving and higher statistical
throughput.
Compliant with 3GPP
(WCDMA 99).
Support LTE interleave
function (optional).
Block length of
40-5114 (40-6144 for LTE).
All-synchronous
design using a single clock, except for global asynchronous reset.
Simple processor
interface for easy programming of configuration registers.
Available as verilog
source code or as netlist.
Turbo code decoder general diagram
Implementation
The base decoder is Max Log MAP with LLR scaling. This decoder
gives only -0.1 dB performance compared with MAP/log MAP decoders,
but ~40% smaller.
Performance
Block size of 5114 bits, rate 1/3.
Ordering information
Turbo Code decoder available as verilog source code or as EDIF
netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog
source code or verilog EDIF netlist.
Verilog
testing environment.
Matlab
model.
Documentation.
For more information please contact
us
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