 Implements
the WiMAX IEEE802.16e/m specifications.
All 802.16 block
sizes (40-4800) are supported.
Block-by-block change
of encoder block size.
No internal memory
is needed.
All-synchronous
design using a single clock, except for global asynchronous reset.
Available as verilog
(optional VHDL) source code or as netlist.
download
product brief
Ordering information
WiMAX Turbo code encoder available as verilog source code or as
EDIF netlist for Xilinx/Altera FPGAs families.
Delivery includes:
Verilog/VHDL
source code or verilog EDIF netlist.
Verification
environment.
Matlab
model.
Documentation.
For more information please
contact
us
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