The IEEE 802.3an LDPC Decoder core performs
iterative decoding of channel data that has been encoded as described
in the IEEE 802.3an standard.
The high throughput required from the decoder and the specific
structure of the IEEE802.3an LDPC code require unique solutions
in order to facilitate an efficient high throughput, low complexity
and low power decoder core.
TurboBest's IEEE802.3an LDPC decoder core is based on a proprietary
algorithmic solution accompanied by a specifically tailored decoder
architecture for the IEEE802.3an LDPC code. These provide a very
efficient, low complexity and low power decoder core supporting
the required high throughput.
The decoder implementation supports streaming mode with coded
bit rate of 6400 Mbits/sec.
The decoder implements a fixed point version of Belief Propagation
(BP) decoding algorithm, providing negligible performance loss
compared to a floating point implementation (less than 0.1dB).
Download:
LDPC 802.3an 10GBASE-T encoder/decoder
Key Features:
 Based
on a proprietary algorithmic solution.
Novel
architecture reaches very low gate count.
Internal
double buffer for continuous decoding with maximum efficiency.
Programmable
number of iterations, support resolution of 1/48 iteration.
Internal
convergence test stops the decoder when data is fully recovered
(0 errors).
Decoded
data rate exceeds 6400 Mbit/s at 400-600 MHz clock frequency.
Code
synthesizable to ASIC 130nm/90nm technology or lower.
BER
of 1E-12 at 23.5dB with constant delay of 0.32 µsec.
Performance graph
Fig
1. decoding gain for 6400 Mbit/sec with constant delay of 0.32
µsec.
Ordering information
The LDPC decoder available as verilog source code.
Delivery includes:
Verilog
source code.
Verilog
test bench.
Matlab
model.
Synthesis
script for Synopsys Design Compiler
Documentation.
For more information please contact
us
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