The IEEE 802.3an LDPC Encoder core performs
encoding as described in the IEEE 802.3an standard.
Flexible architecture supports wide range of clock frequencies.
Download:
LDPC 802.3an 10GBASE-T encoder/decoder 
Key Features:
 Supports
low latency down to 30 ns.
Architecture
supports clock frequencies from 1MHz and up.
Gate
count of 27 Kgates.
All-synchronous
design using a single clock.
Ordering information
The LDPC encoder available as verilog source code.
Delivery includes:
Verilog
source code.
Verilog
test bench.
Matlab
model.
Synthesis
script for Synopsys Design Compiler
Documentation.
For more information please contact
us
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